1. Field of the Invention
The present invention relates to a flip-chip package and a process for fabricating the same. More particularly, the present invention relates to a flip-chip package with electrically conductive adhesive bumps disposed between a chip and a substrate, and to a process for fabricating the same.
2. Description of the Related Art
Flip-chip (FC) interconnect technology has been widely used in the package industry because it facilitates reduction of package area, shortening of signal transmission paths, and fabrication of package structures having high pin counts. In a FC packaging process, a chip is provided with bonding pads disposed on the active surface thereof and arranged in an area array, and bumps are disposed on the bonding pads. Then, the chip is flipped and situated over a carrier, and the bonding pads on the chip and the bump pads on the carrier are electrically and mechanically connected via the bumps. Consequently, the chip is electrically connected to the carrier via the bumps, and further to outer electronic devices via the inner circuits of the carrier. Among all types of package structures utilizing the FC technology, the flip-chip ball grid array (FC/BGA) package and the flip-chip pin grid array (FC/PGA) package are frequently used.
FIG. 1 illustrates a cross-sectional view of a conventional flip-chip package. As shown in FIG. 1, the flip-chip package 100 includes a substrate 110, bumps 120 and a chip 130. The substrate 110 has a top surface 112, a bottom surface 114 opposite to the top surface 112, and bump pads 116 thereon. In addition, the chip 130 has an active surface 132, a back surface 134 opposite to the active surface 132, and bonding pads 136 thereon. The active surface 132 of the chip 130 is the surface formed with the active devices (not shown) of the chip 130. The bonding pads 136 are disposed on the active surface 132 opposite to the bump pads 116 serving as a medium for signal input/output, wherein each bump 120 electrically and mechanically connects a pair of bonding pad 136 and bump pad 116. Thereby, the signals from the chip 130 can be transmitted to the substrate 110 via the bumps 120, and further to an outer electronic apparatus like a printed circuit board (PCB) or a main board via contacts (not shown) disposed on the bottom surface 114 of the substrate 110.
Ordinary types of bump include solder bump, gold bump, electrically conductive adhesive bump and polymer bump, wherein the solder bump is the most popular one, but is also relatively complicated and expensive in fabrication. Referring to FIG. 1, solder bumps 120 are conventionally fabricated with the following steps. An under-bump metallurgy (UBM) 138 composed of multi metal layers is formed on the bonding pads 136 on the chip 130, wherein the metal layers usually include an adhesion layer constituted of Sb, W, Ni, Au, Cu or the alloys thereof, a barrier layer and a wetting layer that are formed with evaporation or sputtering. Thereafter, solder bumps 120 are formed on the under-bump metallurgy 138 on the bonding pads 136 by using a printing method or an electric-plating method, and are melted into spherical bumps in a reflow step and then cooled. The flux (not shown) on the surfaces of the solder bumps 120 are cleaned, and then the chip 130 is electrically and mechanically connected to the substrate 110 via the solder bumps 120. However, since the equipment for fabricating solder bumps is quite expensive and the fabricating process is relatively complicated, flip-chip packages cannot be fabricated with low cost in the prior art.